1. Field of the Invention
The invention relates generally to semiconductor integrated circuit devices, and more particularly, to a semiconductor integrated circuit device comprising external terminals.
2. Description of the Background Art
FIGS. 13 and 14 are examples showing the pin arrangements of static RAMs (Random Access Memory) of a 1M word.times.1 bit organization and a 256K word.times.4 bit organization mounted on packages.
In the static RAM of FIG. 13, pins 1-6, pins 8-11, pins 17-20, pins 22-27 are address input terminals having an address signal A applied, and pin 12 is a data output terminal providing data Q. Pin 13 is a read/write control terminal having a read/write control signal W applied. The read/write control signal W indicates writing in the "L" level, and reading in the "H" level. Pin 14 is a ground terminal having a ground potential of Vss (generally 0 V) applied, and pin 15 is a chip select terminal having a chip select signal CS applied. The chip select signal CS indicates a selected state in the "L" level, and a non-selected state or a stand-by state in the "H" level. Pin 16 is a data input terminal for the input of data D. Pin 28 is a power supply terminal having a power supply potential of Vcc (generally 5 V) applied. Pins 7 and 21 are unconnected terminals.
In the static RAM of the FIG. 14, pin 12 is an address signal input terminal, pin 13 is a chip select terminal, pin 15 is a read/write control terminal, and pins 16-19 are data input/output terminals for the input/output of data. The other pins are similar to those of the static RAM of FIG. 13.
In conventional static RAMs, devices with different word organizations such as 1M word.times.1 bit or 256K word.times.4 bit have different pin arrangements as shown in FIGS. 13 and 14.
The testing of the aforementioned RAMs is considered. The address of 256k is necessary for selecting all the addresses at the time of the testing of the 256k word.times.4 bit organization RAM. At the time of the testing of the 1M word.times.1 bit organization RAM, the addresses of 1M is required to select all the addresses. When the conventional so-called N pattern such as march and checker board test patterns are used, the testing time of a 1M word.times.1 bit organization RAM is four times longer than that of a 256K word.times.4 bit organization RAM. When the N.sup.2 pattern such as galloping test patterns are used, the testing time will be 16 times longer. It is appreciated that even when the RAM of the 1M word.times.1 bit organization and the RAM of the 256K word.times.4 bit organization each have the same memory capacity of 1M bit, the testing time differs due to the difference in word organization.
A semiconductor memory device capable of switching the word organization for reducing the testing time is described in Japanese Patent Laying-Open No. 1-134790 (a corresponding U.S. Pat. No. 4,907,203). This semiconductor memory device is switched to a 1M word.times.1 bit organization RAM during general use, and to a 256K.times.4 bit organization RAM during testing, by externally applied control signals.
Referring to FIGS. 15-25, this semiconductor memory device will be described.
FIG. 15 is a diagram showing the pin arrangement of a semiconductor memory device mounted on a package capable of switching the word organization.
Pins 1-6, pins 8-11, pin 20, and pins 22-27 have an address signal A applied at the time of both the 1M word.times.1 bit organization (hereinafter referred to as .times.1 organization) and the 256K word.times.4 bit organization (hereinafter referred to as .times.4 organization). Pin 14 has ground potential Vss (generally 0 V) applied at the time of .times.1 organization and also at the .times.4 organization, while pin 28 has a power supply potential Vcc (generally 5 V) applied at the time of both the .times.1 organization and .times.4 organization. Pin 12 outputs data Q at the time of .times.1 organization, and has an address signal A applied during .times.4 organization. Pin 13 has a read/write control signal W applied at the time of .times.1 organization, while a chip select signal CS is applied at the time of .times.4 organization. Pin 15 has a chip select signal CS applied at the time of .times.1 organization, while a read/write control signal W is applied at the time of .times.4 organization. Pin 16 has data D applied at the time of .times.1 organization, while data D is applied or data Q is outputted at the time of .times.4 organization. Pins 17-19 have an address signal A applied at the time of .times.1 organization, while data D is applied or data Q outputted at the time of .times. 4 organization. Pin 21 has a switching signal B1/B4 applied at the time of both the .times.1 organization and .times.4 organization.
In this semiconductor memory device, the function of each pin is switched so that the .times.4 organization is set when the switching signal B1/B4 is at the "L" level, and the .times.1 organization set when the switching signal B1/B4 is at the "H" level.
This semiconductor memory device has the circuit described later, which is formed on one semiconductor chip where a plurality of pads are connected to pins 1-28 of the package of FIG. 15 by bonding wire on the semiconductor chip.
FIGS. 16 and 17 are block diagrams showing the means for switching the functions of pins 12, 13, 15, 16 and pins 17-19.
In FIGS. 16 and 17, pads 12p, 13p, 15p-19p are connected to pins 12, 13, 15-19 of FIG. 1, respectively.
When the switching signal B1/B4 is at the "L" level, an address signal A applied to pad 12p is transmitted to the internal circuit via an address input buffer 61. When the switching signal B1/B4 is at the "H" level, data Q applied from the internal circuit is transmitted to pad 12p via a data output buffer 62.
When the switching signal B1/B4 is at the "L" level, the chip select signal CS applied to pad 13p is applied to a CS buffer 64 via an input first stage 63, to be further transferred to the internal circuit. At this time, the read/write control signal W applied to pad 15p is provided to a WE buffer 65 via input first stage 63 to be further transferred to the internal circuit. On the contrary, when the switching signal B1/B4 is at the "H" level, the read/write control signal W applied to pad 13p is transferred to the internal circuit via input first stage 63 and WE buffer 65, while the chip select signal CS applied to pad 15p is transferred to the internal circuit via input first stage 63 and CS buffer 64.
Furthermore, when the switching signal B1/B4 is at the "L" level, data D applied to pad 16p is either transferred to the internal circuit via a data input buffer 66 for .times.4 organization, or data Q applied from the internal circuit is transferred to pad 16p via data output buffer 62. When the switching signal B1/B4 is at the "H" level, data D applied to pad 16b is transferred to the internal circuit via a data input buffer 67 for .times.1 organization.
When the switching signal B1/B4 is at the "L" level, data D applied to pad 17p is either transferred to the internal circuit via data input buffer 66, or data Q applied from the internal circuit is transferred to pad 17p via data output buffer 62. When the switching signal B1/B4 is at the "H" level, the address signal A applied to pad 17p is transferred to the internal circuit via address input buffer 61.
The circuit connected to pads 18p and 19p is likewise to the circuit connected to pad 17p.
Circuit diagrams of each portion of the semiconductor memory device is shown more specifically in FIGS. 18-25. In these diagrams, N51-N78 indicate n channel transistors, while P51-P81 indicate p channel transistors.
FIG. 18 is a circuit diagram of the address input buffer 61 shown in FIGS. 16 and 17.
First and second control signals E, E are complementary signals, and coupled to the switching signal B1/B4 and the inverted switching signal B4/B1, respectively. The address input buffer 61 is activated when the first control signal E is at the "H" level, and inactivated when the first control signal E is at the "L" level.
When the first control signal E is at the "L" level and the second control signal E is at the "H" level, transistors N51, P51 are turned off while transistor P52 is turned on. This causes a signal of the "H" level to be applied to one input terminal of a NOR circuit 68. Therefore, the output of NOR circuit 68 is fixed to the "L" level. As a result, the output of NOR circuit 68 is not affected by the address signal A applied to the other input terminal. At this time, since transistors N52 and P54 are turned off, node a connected to the internal circuit is brought to a floating state.
A chip select signal CS1 is generated in the chip in response to a chip select signal CS applied externally.
FIG. 19 is a circuit diagram of the input first stage 63 of FIG. 16.
The first and second select signals E1/E2 and E2/E1 are signals complementary to each other and coupled to the switching signal B1/B4 and the inverted switching signal B4/B1, respectively.
When the first select signal E1/E2 is at the "H" level, transistors N56 and P58 are turned on, while transistors N54 and P56 are turned off. This causes the inverted signal of the output of NOR circuit 69 to be provided to node b, whereby node c is brought to a floating state. When the first select signal E1/E2 is at the "L" level, node b is brought to a floating state, and the inverted signal of the output from NOR circuit 69 is provided to node c. Accordingly, the inverted signal of the output from NOR circuit 69 is provided to node b or node c in response to the first and second select signals E1/E2, E2/E1.
A chip select signal CS or a read/write control signal W is applied to one input terminal of NOR circuit 69, while a signal provided internally of the chip such as chip select signal CS1 or a fixed potential is applied to the other input terminal of NOR circuit 69.
FIG. 20 is a block diagram of a data input buffer 66 for .times.4 organization shown in FIGS. 16 and 17.
The data input buffer 66 for .times.4 organization is activated only when the switching signal B1/B4 is at the "L" level.
The switching signal B1/B4 and the inverted switching signal B1/B4 are signals complementary to each other. When the switching signal B1/B4 is at the "H" level and the inverted switching signal B1/B4 is at the "L" level, transistors N58, P59 and N59, P62 are turned off, while transistor P60 is turned on. Accordingly, the output of NOR circuit 70 is fixed to the "L" level, and the buffer output WD from node d is brought to a floating state.
On the contrary, when the switching signal B1/B4 is at the "L" level, and the inverted switching signal B1/B4 is at the "H" level, transistors N58, P59 and N59, P62 are turned on, while transistor P60 is turned off. This causes the output of NOR circuit 70 to change in response to the change of data D, with the buffer output WD following.
Four data input buffers 66 for .times.4 organization are provided in the chip to obtain four buffer outputs WD at the time of .times.4 organization.
FIG. 21 is a block diagram of a data input buffer 67 for .times.1 organization shown in FIG. 16.
The data input buffer 67 for .times.1 organization is different from the data input buffer 66 for .times.4 organization in that the switching signal B1/B4 and the inverted switching signal B1/B4 are connected in an opposite manner, with four buffer outputs WD1, WD2, WD3, and WD4 obtained at nodes e, f, g, and h, respectively, from the output of inverter 45. The data input buffer 67 for .times.1 organization activates when the switching signal B1/B4 is at the "H" level (at the time of .times.1 organization).
FIG. 22 is a circuit diagram of the data output buffer 62 shown in FIGS. 16 and 17.
When the output buffer control signal OE is at the "L" level, the output of an NAND circuit 78 is at the "H" level and the output of a NOR circuit 77 is at the "L" level. This turns transistor N70, P73 off. Consequently, node i is brought to a floating state, that is, a high impedance state.
On the contrary, when the output buffer control signal OE is at the "H" level, data RDA applied from a memory cell is inverted by NAND circuit 78 and NOR circuit 77 to be transferred to the gates of transistors P73, N70. This causes the output from node i to vary in response to data RDA.
The data output buffers 62 for .times.1 organization and .times.4organization both have the same circuit structure. At the time of .times.1 organization, an output buffer control signal OE of the "H" level is applied to the .times.1 organization output buffer 62, and an output buffer control signal OE of the "L" level is applied to the .times.4 organization data output buffer 62. At the time of .times.4 organization, the output buffer control signal OE of the reversed levels are applied. Thus, the activation of the data output buffer 62 can be switched between .times.1 organization and .times.4 organization.
FIG. 23 is a block diagram showing the internal circuit of the semiconductor memory device. A memory cell array 80 includes a plurality of memory cells arranged in a plurality of rows and columns. A row decoder 79 selects one row of memory cell array 80 in response to a plurality of address signals RA applied via a plurality of address input buffers. A column decoder 81 selects four columns of memory cell array 80 in response to a plurality of address signals CA applied via a plurality of address input buffers.
At the time of reading, data is read out from the four memory cells selected by row decoder 79 and column decoder 81. The four sense amplifiers 82 senses and amplifies these data and applies them to a signal switching circuit 84 via read data buses RD1-RD4. The signal switching circuit 84 switches the connection of the read data bus between the .times.4 organization and the .times.1 organization in response to the switching signal B1/B4 and the inverted switching signal B4/B1.
At the time of .times.4 organization, the four data readout in read data buses RD1-RD4 are applied to a data output buffer 85 for .times.4 organization via read data buses RDA1-RDA4. At the time of .times.1 organization, one of the data of the read data buses RD1-RD4 is applied to the data output buffer 86 for .times.1 organization via read data bus RDA in response to select signals IOS1-IOS4. The select signals IOS1-IOS4 are generated from two bits of the address signal A.
At the time of writing, data is applied to four data input buffers 87, or to one data input buffer 89. At the time of .times.4 organization, the data applied to four data input buffers 87 are provided to four writing circuits 83 via writing data buses WD1-WD4, respectively. These data are written into four memory cells selected by row decoder 79 and column decoder 81.
At the time of .times.1 organization, the data applied to data input buffer 89 is applied to four writing circuits 83 via four writing data buses WD1-WD4. One data among the four is selected by two bits of the address signal A. This data is written into a memory cell selected by row decoder 79 and column decoder 81.
FIG. 24 is a circuit diagram showing the structure of the signal switching circuit 84 of FIG. 23.
Transistors N71-N78 and transistors P74-P81 form eight transfer gates T1-T8.
When the switching signal B1/B4 at the "L" level, and the inverted switching signal B4/B1 is at the "H" level, the transfer gates T1-T4 are turned on. Also, the outputs of NOR circuit 90 are brought to the "L" level to turn transfer gates T5-T8 off. Thus, read data buses RD1-RD4 are connected to read data buses RDA1-RDA4 via transfer gates T1-T4, respectively.
On the contrary, when the switching signal B1/B4 is at the "H" level, and the inverted switching signal B4/B1 is at the "L" level, transfer gates T1-T4 are turned off. Also, one output of NOR circuit 90 is brought to the "H" level in response to select signals IOS1-IOS2. This turns one of the transfer gates T5-T8 on. As a result, one of the read data buses RD1-RD4 is connected to the read data bus RDA via a transfer gate.
FIG. 25 is a diagram showing an example of a switching signal generating circuit.
The switching signal B1/B4 applied to pad 21p is inverted to become an inverted switching signal B4/B1 by an inverter 92. This is further inverted by inverter 93 to become a switching signal B1/B4.
Using this circuit, it is possible to change the word organization by the signal externally applied to pin 21.
In the semiconductor memory device of FIG. 15, pins 1-11 and pins 20-27 each have a single function, while pin 12, pin 13 and pins 15-19 have a plurality of functions. Pins with such multiplexed functions have a plurality of circuits connected to the corresponding pads, as shown in FIGS. 16 and 17. Therefore, there is a difference in input capacitance between pins having multiplexed functions and pins having only one function.
For example, the input capacitance of pin 19 having an address signal A applied at the time of .times.1 organization is different from that of pin 20 having an address signal A applied. This means that the transfer speed of the address signal A applied to pin 19 differs from the transfer speed of the address signal A applied to pin 20. Since the access time of the semiconductor memory device is determined by the address signal A having a slow transfer speed, the access time during .times.1 organization and the access time during .times.4 organization will differ.
Thus, by changing the word organization, the characteristic of the semiconductor memory device will change. For example, in the case the semiconductor memory device is tested under the state of .times.4 organization for the purpose of reducing the testing time, the testing result will differ from that of the semiconductor memory device under the state of the .times.1 organization. Consequently, a correct testing result can not be obtained.
Also, since the input capacitance of each pin varies, the stray capacitance of the signal wiring on the board will differ when the semiconductor memory device is packaged on the board. This generates speed differences in the signals on the board, that is to say, skew occurs. While skew is generated, it is necessary to substantially lower the operating speed of the system and increase the operating cycle, which becomes the cause of lowering the performance of the system.